Layout driven FPGA packing algorithm for performance optimization

被引：2

作者：

Mo, Linfeng ^{[1
]}

Wu, Chang ^{[1
]}

He, Lei ^{[1
,2
]}

Chen, Gengsheng ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China

[2] Univ Calif Los Angeles, Elect Engn Dept, Los Angeles, CA 90024 USA

来源：

IEICE ELECTRONICS EXPRESS | 2017年 / 14卷 / 11期

关键词：

FPGA; packing; placement; layout;

D O I：

10.1587/elex.14.20170419

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

FPGA is a 2D array of configurable logic blocks. Packing is to pack logic elements into device specific configurable logic blocks for subsequent placement. The traditional fixed delay model of inter and intra cluster delays used in packing does not represent post-placement delays and often leads to sub-optimal solutions. This paper presents a new layout driven packing algorithm, named LDPack, based on a novel pre-packing placement for performance optimization. Our results show that after placement and routing LDPack outperforms Xilinx ISE MAP with 8% reduction in area and 5.22% smaller critical path delay, at the cost of 18% more runtime in average.

引用

页数：10

共 50 条

[1] Physical Information Driven Packing Method in FPGA [J].

Sui, Wentao ;

Dong, Sheqin ;

Bian, Jinian ;

Hong, Xianlong .

PROCEEDINGS OF THE 11TH JOINT CONFERENCE ON INFORMATION SCIENCES, 2008,

[2] GOLDS: Genetic Algorithm-based Optimization of Custom FPGA Architecture Layout Design for Secure Silicon [J].

Nandi, Pratyush ;

Mishra, Anubhav ;

Rao, Madhav .

PROCEEDING OF THE GREAT LAKES SYMPOSIUM ON VLSI 2024, GLSVLSI 2024, 2024, :92-97

[3] A data-driven evolutionary algorithm for wind farm layout optimization [J].

Long, Huan ;

Li, Peikun ;

Gu, Wei .

ENERGY, 2020, 208

[4] Performance and wirability driven layout for row-based FPGAs [J].

Nag, S ;

Roy, K .

VLSI DESIGN, 1998, 7 (04) :353-364

[5] Power-Aware FPGA Packing Algorithm [J].

Yang, M. ;

Xu, Hongying ;

Almaini, A. E. A. .

2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, :817-+

[6] Algorithm for yield driven correction of layout [J].

Wang, Y ;

Cai, YC ;

Hong, XL ;

Zhou, QA .

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 5, PROCEEDINGS, 2004, :241-244

[7] UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing [J].

Li, Wuxi ;

Dhar, Shounak ;

Pan, David Z. .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (04) :869-882

[8] An Improved Parallel Genetic Algorithm Based on Particle Swarm Optimization and Its Application to Packing Layout Problems [J].

Zhao, Fengqiang ;

Li, Guangqiang ;

Du, Jialu ;

Guo, Chen ;

Hu, Hongying .

PROCEEDINGS OF THE 2012 WORLD CONGRESS ON INFORMATION AND COMMUNICATION TECHNOLOGIES, 2012, :1209-1214

[9] The Application of Layout Heuristic Optimization Algorithm in Operational Model [J].

Liu, Shuyuan .

MATERIALS PROCESSING AND MANUFACTURING III, PTS 1-4, 2013, 753-755 :1914-1917

[10] An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs [J].

Li, Zijun ;

Zhu, Ziran ;

He, Huan ;

Chen, Jianli .

INTEGRATION-THE VLSI JOURNAL, 2024, 94

← 1 2 3 4 5 →