Ultra Low Power Flash ADC for UWB Transceiver Applications

被引：0

作者：

Masoumi, Mohammad ^{[1
]}

Markert, Erik ^{[1
]}

Heinkel, Ulrich ^{[1
]}

Gielen, Georges ^{[2
]}

机构：

[1] TU Chemnitz, Chair Circuit & Syst Design, Chemnitz, Germany

[2] KULEUVEN, Dept Elect Engn, Leuven, Belgium

来源：

2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2 | 2009年

关键词：

A/D Converter; Kickback noise; Resistor ladder; comparator; encoder; CONVERTER; CMOS;

D O I：

10.1109/ECCTD.2009.5275135

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper a low power, 4-bit, 50 MHz flash ADC in 130nm technology is presented. Power consumption is the most important objective in this ADC. Two blocks, S/H and Latch, can be omitted in this ADC because of the comparator and encoder structures. Flash ADC has a peak SNDR of 23.47dB at Nyquist frequency while the power consumption is 130 mu W with a binary code encoder. This reduces to 115 mu W if output data are in Gray code. The proposed ADC achieves 0.1625 pJ per conversion-step if the output is binary.

引用

页码：41 / +

页数：2

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