32-bit RISC CPU Based on MIPS

被引:0
|
作者
Yi, Kui [1 ]
Ding, Yue-Hua [1 ]
机构
[1] WuHan Polytech Univ, Dept Comp Sci & Informat Engineer, Wuhan 430023, Hubei Province, Peoples R China
来源
PROCEEDINGS OF THE 2009 SECOND PACIFIC-ASIA CONFERENCE ON WEB MINING AND WEB-BASED APPLICATION | 2009年
关键词
MIPS; Data Flow; Data Path; Pipeline;
D O I
10.1109/WMWA.2009.62
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, through analysis of function and working theory of RISC CPU instruction decoder module, we design instruction decoder module of 32-bit CPU. The instruction decoder includes register file, write back data to register file, sign bit extend, relativity check, and it is simulated on QuartusII successfully
引用
收藏
页码:124 / 128
页数:5
相关论文
共 50 条
  • [23] A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer
    Chen JianWu
    Wu DanYu
    Zhou Lei
    Wu Jin
    Jin Zhi
    Liu XinYu
    CHINESE SCIENCE BULLETIN, 2012, 57 (19): : 2480 - 2487
  • [24] A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer
    CHEN JianWu1
    2 Key Laboratory of Microelectronics Devices & Integrated Technology
    Science Bulletin, 2012, (19) : 2484 - 2491
  • [25] An efficient design of FSM based 32-bit unsigned high-speed pipelined multiplier using Verilog HDL
    Abdullah-Al-Kafi
    Rahman, Atul
    Mahjabeen, Bushra
    Rahman, Mahmudur
    2014 INTERNATIONAL CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (ICECE), 2014, : 164 - 167
  • [27] An open source synthesisable model in VHDL of a 64-bit MIPS-based processor
    Kelly, Daniel R.
    Phillips, Braden J.
    Al-Sarawi, Said
    SMART STRUCTURES, DEVICES, AND SYSTEMS III, 2007, 6414
  • [29] Pipeline Design of Transformation between Floating Point Numbers based on IEEE754 Standard and 32-bit Integer Numbers
    Hu, Zheng-wei
    Duan, Dong-xing
    Xie, Zhi-yuan
    Yang, Xing
    IITSI 2009: SECOND INTERNATIONAL SYMPOSIUM ON INTELLIGENT INFORMATION TECHNOLOGY AND SECURITY INFORMATICS, 2009, : 92 - 96