Vertical Field effect transistor with sub-15nm gate-all-around on Si nanowire array

被引：0

作者：

Larrieu, G. ^{[1
]}

Guerfi, Y. ^{[1
]}

Han, X. L. ^{[2
]}

Clement, N. ^{[2
]}

机构：

[1] CNRS, LAAS, 7 Ave Colonel Roche, F-31077 Toulouse, France

[2] CNRS, IEMN, UMR 8520, F-59652 Villeneuve Dascq, France

来源：

ESSDERC 2015 PROCEEDINGS OF THE 45TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2015年

关键词：

3D transistors; nanowire; gate-all-around; MOS scaling;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations both in processing (layer engineering at nanoscale), in electrical properties (high electrostatic control, low defect level, multi-Vt platform) in the fabrication of CMOS inverters and in the perspective of ultimate scaling.

引用

页码：202 / 205

页数：4

共 9 条

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