Speculative versioning cache

Dependences among loads and stores whose addresses are unknown hinder the execution of instruction level parallelism during the execution of a sequential program. Such ambiguous memory dependences carl be overcome by memory dependence speculation which enables a load or store to be speculatively executed before the addresses of all preceding loads and store are known. Furthermore, multiple speculative stores to a memory location create multiple speculative versions of the location. Program order among the speculative versions must be tracked To maintain sequential semantics. A previously proposed approach, the Address Resolution Buffer (ARB) uses a centralized buffer to support speculative versions. Our ply proposal, called the Speculative Versioning Cache(SVC), uses distributed cadres to eliminate the latency and bandwidth problems of the ARE. The SVC conceptually unifies cache coherence and speculative versioning by using an organization similar, to snooping bus-based coherent caches. A preliminary evaluation for the Multiscalar architecture shows that hit latency is an important factor affecting performance, and private cache solutions trade-off hit rate for hit latency.