Reduced-kickback regenerative current comparator for high-speed switched-current pipeline analogue-to-digital converters

A reduced-kickback regenerative current comparator based on a master-slave structure is presented. The master and slave comparators first operate concurrently but, soon, the master's operation is inhibited to prevent the extreme voltage surges, or kickback, from disturbing the driving memory while the slave circuit is allowed to regenerate and produce a valid digital output. Simulations indicate that practically no accuracy degradation in the driving memory cell is detected whereas the same operation using the elementary comparator disturbs the accuracy by more than 4 bits. Designed in a standard 0.35 pot 3.3 V digital CMOS technology, the master-slave comparator achieves a sampling speed of 100 MS/s with 7.5 bit resolution, while dissipating 290 muW of power from a single 1.8 V supply.