Analog Operation of Junctionless Nanowire Transistors down to Liquid Helium Temperature

被引：0

作者：

Trevisoli, Renan ^{[1
]}

de Souza, Michelly ^{[1
]}

Doria, Rodrigo T. ^{[1
]}

Kilchtyska, Valeriya ^{[2
]}

Flandre, Denis ^{[2
]}

Pavanello, Marcelo A. ^{[1
]}

机构：

[1] Ctr Univ FEI, Elect Enigeering Dept, Sao Bernardo Do Campo, Brazil

[2] Catholic Univ Louvain, ICTEAM Inst, Louvain la Neuve, Belgium

来源：

2014 11TH INTERNATIONAL WORKSHOP ON LOW TEMPERATURE ELECTRONICS (WOLTE) | 2014年

基金：

巴西圣保罗研究基金会;

关键词：

Junctionless Transistors; Output Conductance; Voltage Gain;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The aim of this work is to analyze the analog operation of Junctionless Nanowire Transistors at temperatures down to liquid helium temperature. The analysis is performed in terms of the transconductance, open loop voltage gain and output conductance for experimental long channel devices. It is shown that the temperature reduction can affect significantly the analog performance of the devices.

引用

页码：53 / 56

页数：4

共 16 条

[1] Device modeling at cryogenic temperatures: Effects of incomplete ionization [J].

Akturk, Akin ;

Allnutt, Jeffrey ;

Dilli, Zeynep ;

Goldsman, Neil ;

Peckerar, Martin .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (11) :2984-2990

[2]

[Anonymous], FINFETS OTHER MULTIG

[3] Junctionless Nanowire Transistor (JNT): Properties and design guidelines [J].

Colinge, J. P. ;

Kranti, A. ;

Yan, R. ;

Lee, C. W. ;

Ferain, I. ;

Yu, R. ;

Akhavan, N. Dehdashti ;

Razavi, P. .

SOLID-STATE ELECTRONICS, 2011, 65-66 :33-37

[4]

Colinge J. P., 2009, IEEE INT SOI C

[5]

Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/nnano.2010.15, 10.1038/NNANO.2010.15]

[6] Cryogenic Operation of Junctionless Nanowire Transistors [J].

de Souza, Michelly ;

Pavanello, Marcelo A. ;

Trevisoli, Renan D. ;

Doria, Rodrigo T. ;

Colinge, Jean-Pierre .

IEEE ELECTRON DEVICE LETTERS, 2011, 32 (10) :1322-1324

[7] Analysis of the parasitic S/D resistance in multiple-gate FETs [J].

Dixit, A ;

Kottantharayil, A ;

Collaert, N ;

Goodwin, M ;

Jurezak, M ;

De Meyer, K .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (06) :1132-1140

[8]

Doria R.T., 2010, P SOI C

[9]

Doria R. T., 2020, JICS, V7, P121, DOI [10.29292/jics.v7i2.364, DOI 10.29292/JICS.V7I2.364]

[10] Junctionless Multiple-Gate Transistors for Analog Applications [J].

Doria, Rodrigo Trevisoli ;

Pavanello, Marcelo Antonio ;

Trevisoli, Renan Doria ;

de Souza, Michelly ;

Lee, Chi-Woo ;

Ferain, Isabelle ;

Akhavan, Nima Dehdashti ;

Yan, Ran ;

Razavi, Pedram ;

Yu, Ran ;

Kranti, Abhinav ;

Colinge, Jean-Pierre .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (08) :2511-2519

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