On hardware implementations of DCT and quantization blocks for H.264/AVC

被引：4

作者：

Kordasiewicz, Roman ^{[1
]}

Shirani, Shahram ^{[1
]}

机构：

[1] McMaster Univ, Dept Elect & Comp Engn, Hamilton, ON L8S 4K1, Canada

来源：

JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2007年 / 47卷 / 03期

关键词：

H.264/AVC; JVT; MPEG4; integer DCT; Quantization; Xilinx Virtex 2-Pro; PPC; FPGA; architecture; hardware implementations;

D O I：

10.1007/s11265-006-0043-4

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

H.264/AVC also known as MPEG 4 part 10 or JVT, is a recently established video coding standard by the Joint Video Team (JVT) of the ISO/IEC MPEG and ITU-T VCEG. The main goal of the paper is to give a broader understanding of the design considerations for the transform and quantization blocks from H.264/AVC, by presenting area and speed optimized implementations of these blocks. The area optimized design can be used in low performance applications like mobile devices, while the speed optimized designs can be used in high definition encoders. Various designs with these blocks were synthesized with 0.18 mu m TSCM technology and were also implemented on a Xilinx FPGA. The resulting gate counts were anywhere from 294 to 47,762 gates and the throughput was anywhere from 6 to 2,552 M pixels/s depending on block and optimization. In addition, a system on a programmable chip implementation of the DCT and quantization blocks is presented, which uses the Xilinx Virtex II-Pro's FPGA and its Power PC. Using this system it is possible to process 0.8 M pixels/s.

引用

页码：189 / 199

页数：11