A system-on-a-chip for pattern recognition -: Architecture and design methodology

被引：0

作者：

Aberbour, M ^{[1
]}

Mehrez, H ^{[1
]}

Durbin, F ^{[1
]}

Haussy, J ^{[1
]}

Lalande, P ^{[1
]}

Tissot, A ^{[1
]}

机构：

[1] UPMC Paris 6, ASIM, Lab LIP6, F-75252 Paris 05, France

来源：

5TH INTERNATIONAL WORKSHOP ON COMPUTER ARCHITECTURES FOR MACHINE PERCEPTION, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/CAMP.2000.875973

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

We address in this paper the design and specification of a heterogeneous architecture of a SOC (System-On-a-Chip) for pattern recognition. Once the algorithms involved presented, we investigate the hardware/software codesign methodology, the system architecture and finally the VLSI physical integration. We conclude by giving results on the performance of the system regarding recognition rate and VLSI characteristics.

引用

页码：155 / 162

页数：8