Modeling of ΔIBL due to random telegraph noise with considering bit-line interference in NAND flash memory

被引:0
|
作者
Joe, Sung-Min [1 ]
Bae, Jong-Ho [1 ]
Park, Chan Hyeong [2 ]
Lee, Jong-Ho [1 ]
机构
[1] Seoul Natl Univ, Interuniv Semicond Res Ctr, Sch Elect & Comp Engn, Seoul 151742, South Korea
[2] Kwangwoon Univ, Dept Elect & Commun Engn, Seoul 139701, South Korea
关键词
model; random telegraph noise; bit-line interference; bit-line current fluctuation; NAND flash memory;
D O I
10.1088/0268-1242/29/12/125013
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Bit-line (BL) current fluctuation (Delta I-BL = high I-BL - low I-BL) of the trap position is modeled as a parameter of the state (program or erase) of adjacent BL cells which affects the current density distribution appreciably. To model Delta I-BL, we extracted the integrated electron current density (J(0) = f(z)) and the electric blockade length (L-t) by considering the effect of the interference of adjacent cells. A characteristic function (g(z)) which has a Gaussian functional form is defined based on L-t and the trap position within the tunneling oxide from the channel surface (x(T)). Finally, Delta I-BL is extracted through the integration of f(z) and g(z). Our model predicts accurately the Delta I-BL with the trap position as a parameter of the state of BL cells, showing good agreement with 3D simulation data.
引用
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页数:5
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