An FPGA-Based Real-Time Event Sampler

被引：0

作者：

Penneman, Niels ^{[1
,2
]}

Perneel, Luc ^{[3
]}

Timmerman, Martin ^{[1
]}

De Sutter, Bjorn ^{[1
,2
]}

机构：

[1] Vrije Univ Brussel, Dept Elect & Informat, Pl Laan 2, B-1050 Brussels, Belgium

[2] Univ Ghent, Comp Syst Lab, B-9000 Ghent, Belgium

[3] Dedicated Syst Experts, 421B12 St Pieters Leeuw, Belgium

来源：

RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS | 2010年 / 5992卷

关键词：

real-time testing; event sampling; logic analyzer; FPGA;

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

This paper presents the design and FPGA-implementation of a sampler that is suited for sampling real-time events in embedded systems. Such sampling is useful, for example, to test whether real-time events are handled in time on such systems. By designing and implementing the sampler as a logic analyzer on an FPGA, several design parameters can be explored and easily modified to match the behavior of different kinds of embedded systems. Moreover, the trade-off between price and performance becomes easy, as it mainly exists of choosing the appropriate type and speed grade of an FPGA family.

引用

页码：364 / +

页数：2

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