Power-efficient value speculation for high-performance microprocessors

Improving instruction-level parallelism (ILP) has become one of the greatest challenges in highperformance microprocessor design. Several techniques for counteracting control and data dependencies, based on prediction and speculative execution, have been proposed and their cost and performance trade-offs widely studied. However, in some cases, such as value speculation, power consumption considerations have remained unanalyzed. In this paper we explore the main sources of power dissipation to be considered when value speculation is used and rye propose solutions to reducing this dissipation - reducing the size of the prediction fables, decreasing the amount of extra work due to speculative execution, and reducing the complexity of the out-of-order issue logic -, in order to prove that value speculation can be considered a power efficient technique for future generations of microprocessors.