High density embedded DRAM technology with 0.38μm pitch in DRAM and 0.42μm pitch in LOGIC by W/polySi gate and Cu dual Damascene metallization

被引：10

作者：

Takenaka, N ^{[1
]}

Segawa, M ^{[1
]}

Uehara, T ^{[1
]}

Akamatsu, S ^{[1
]}

Matsumoto, M ^{[1
]}

Kurimoto, K ^{[1
]}

Ueda, T ^{[1
]}

Watanabe, H ^{[1
]}

Matsutani, T ^{[1
]}

Yoneda, K ^{[1
]}

Koshio, A ^{[1
]}

Kato, Y ^{[1
]}

Inuishi, M ^{[1
]}

Oashi, T ^{[1
]}

Tsukamoto, K ^{[1
]}

Komori, S ^{[1
]}

Tomita, K ^{[1
]}

Inbe, T ^{[1
]}

Ohsaki, A ^{[1
]}

Hanawa, T ^{[1
]}

Sakamori, S ^{[1
]}

Shirahata, M ^{[1
]}

Tsuchimoto, J ^{[1
]}

Eimori, T ^{[1
]}

机构：

[1] Matsushita Elect Corp, Semicond Co, ULSI Proc Technol Dev Ctr, Minami Ku, Kyoto 6018413, Japan

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852770

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A high density Embedded DRAM technology has been developed with 0.38 mu m pitch in DRAM and 0.42 mu m pitch in LOGIC/SRAM. This technology includes (1) W/WNx polymetal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2) W-pluged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3) 6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology can realizes both very small, DRAM cell size of 0.29 mu m(2) and SRAM cell size of 2.77 mu m(2) on the same die.

引用

页码：62 / 63

页数：2

共 8 条

[1]

CROWDER S, 1999, VLSI TECH DIG, P105

[2]

Hamada M., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P45, DOI 10.1109/IEDM.1999.823843

[3]

INOHARA M, 1998, VLSI TECH DIG, P64

[4]

KOKUBUN K, 1999, VLSI TECH DIG, P155

[5]

SAMBONSUGI Y, 1998, VLSI TECH DIG, P62

[6]

WOO M, 1998, VLSI, P12

[7]

YANG WS, 1999, VLSI JUN, P13

[8]

Yoshida M., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P41, DOI 10.1109/IEDM.1999.823842

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