3-D Modeling of Fringing Gate Capacitance in Gate-all-around Cylindrical Silicon Nanowire MOSFETs

被引：0
|
作者：
An, TaeYoon [1 ]
Kim, SoYoung [1 ]
机构：
[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon, Gyeonggi Do, South Korea
来源：
2013 18TH INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD 2013) | 2013年
关键词：
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
In this paper, an analytical model for fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs (SNWTs) is proposed. The fringing gate capacitances of the SNWT are divided into three parts: sidewall capacitance C-side; parallel capacitance C-gsd; perpendicular capacitance C-gex. Each capacitance is calculated using the following methods: conformal mapping, integral and non-dimensionalization. The proposed model is verified with a three-dimensional field solver, Raphael. Based on the proposed model, the fringing capacitance can be easily predicted in the vertically and horizontally stacked multi-wire SNWTs.
引用
收藏
页码：256 / 259
页数：4
相关论文
共 50 条
  • [31] Hot carrier and PBTI induced degradation in silicon nanowire gate-all-around SONOS MOSFETs
    Choi, Jin Hyung
    Han, Jin-Woo
    Yu, Chong Gun
    Park, Jong Tae
    MICROELECTRONICS RELIABILITY, 2014, 54 (9-10) : 2325 - 2328
  • [32] Dopant-Segregated Schottky Silicon-Nanowire MOSFETs With Gate-All-Around Channels
    Chin, Yoke King
    Pey, Kin-Leong
    Singh, Navab
    Lo, Guo-Qiang
    Tan, Khing Hong
    Ong, Chio-Yin
    Tan, L. H.
    IEEE ELECTRON DEVICE LETTERS, 2009, 30 (08) : 843 - 845
  • [33] 6-T SRAM Cell Design with Gate-All-Around Silicon Nanowire MOSFETs
    Liao, Yi-Bo
    Chiang, Meng-Hsueh
    Damrongplasit, Nattapol
    Liu, Tsu-Jae King
    Hsu, Wei-Chou
    2013 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), 2013,
  • [34] Fully gate-all-around silicon nanowire CMOS devices
    Institute of Microelectronics, Singapore, Singapore
    Solid State Technol, 2008, 5 (34-37):
  • [35] Gate-All-Around Silicon Nanowire Devices: Are these the Future of CMOS?
    Lo, G. Q.
    Singh, N.
    Rustagi, S. C.
    Buddharaju, K. D.
    Balasubramanian, N.
    Kwong, D. L.
    SIGE, GE, AND RELATED COMPOUNDS 3: MATERIALS, PROCESSING, AND DEVICES, 2008, 16 (10): : 729 - 729
  • [36] Fully gate-all-around silicon nanowire CMOS devices
    Singh, N.
    Buddharaju, K. D.
    Agarwal, A.
    Rustagi, S. C.
    Lo, G. Q.
    Balasubramanian, N.
    Kwong, D. L.
    SOLID STATE TECHNOLOGY, 2008, 51 (05) : 34 - 37
  • [37] Gate-all-around twin silicon nanowire SONOS memory
    Suk, Sung Dae
    Yeo, Kyoung Hwan
    Cho, Keun Hwi
    Li, Ming
    Yeoh, Yun young
    Hong, Ki-Ha
    Kim, Sung-Han
    Koh, Young-Ho
    Jung, Sunggon
    Jang, WonJun
    Kim, Dong-Won
    Park, Donggun
    Ryu, Byung-Il
    2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 142 - +
  • [38] Impact of Gate Asymmetry on Gate-All-Around Silicon Nanovvire Transistor Parasitic Capacitance
    Dong, Xiaoqiao
    Yang, Yuancheng
    Chen, Gong
    Sun, Shuang
    Cai, Qifeng
    Li, Xiaokang
    An, Xia
    Xu, Xiaoyan
    Zhang, Wanrong
    Li, Ming
    2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 296 - 298
  • [39] Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors
    Xiaoqiao Dong
    Ming Li
    Wanrong Zhang
    Yuancheng Yang
    Gong Chen
    Shuang Sun
    Jianing Wang
    Xiaoyan Xu
    Xia An
    Science China Information Sciences, 2020, 63
  • [40] Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors
    Dong, Xiaoqiao
    Li, Ming
    Zhang, Wanrong
    Yang, Yuancheng
    Chen, Gong
    Sun, Shuang
    Wang, Jianing
    Xu, Xiaoyan
    An, Xia
    SCIENCE CHINA-INFORMATION SCIENCES, 2020, 63 (10)
12345