A Test Integration Methodology for 3D Integrated Circuits

被引：22

作者：

Chou, Che-Wei ^{[1
]}

Li, Jin-Fu ^{[1
]}

Chen, Ji-Jan ^{[2
]}

Kwai, Ding-Ming ^{[2
]}

Chou, Yung-Fa ^{[2
]}

Wu, Cheng-Wen ^{[2
]}

机构：

[1] Natl Cent Univ, Dept Elect Engn, Jhongli 320, Taiwan

[2] Ind Technol Res Inst, Informat & Commun Res Lab ICL, Hsinchu 310, Taiwan

来源：

2010 19TH IEEE ASIAN TEST SYMPOSIUM (ATS 2010) | 2010年

关键词：

DESIGN; OPTIMIZATION; CHALLENGES; SILICON;

D O I：

10.1109/ATS.2010.71

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before the volume production of 3D ICs. One of the challenges is the testing of 3D ICs. This paper proposes test integration interfaces for controlling the design-for-test circuits in the dies of a 3D IC. The test integration interfaces can support the pre-bond, known-good stack, and post-bond tests. The minimum number of required test pads of the proposed test interface for pre-bond test using is only four. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the proposed test interfaces for a 3D IC with two dies in which each die implements the function of ITC'99 b19 benchmark is only about 0.15%.

引用

页码：377 / 382

页数：6

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