Integrated substrate technology

被引:5
作者
Chanchani, R [1 ]
Bethke, DT [1 ]
Webb, DB [1 ]
Sandoval, C [1 ]
Wouters, G [1 ]
机构
[1] Sandia Natl Labs, Albuquerque, NM 87123 USA
来源
54TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS | 2004年
关键词
D O I
10.1109/ECTC.2004.1320271
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Advanced micro-systems for national security needs will require miniaturization and integration of RF, digital and analog electronics, optics and MEMS on a single substrate. To meets these demands we have developed an integrated substrate technology using Benzocyclobutene (BCB)/copper (Cu) with embedded thin film passive components. We have developed processes to fabricate BCB/Cu multilayer stack on silicon (Si), alumina (Al2O3) and Low Temperature Co-fired Ceramic (LTCC) wafers. A multi-layer stack of 6 metal layers and 5 BCB layers using 5-micron and 10-micron thick photodefinable BCB dielectric and 2 to 3-micron thick Cu conductor have been demonstrated. The design rules for minimum featured size used were 30-micron vias on 50-micron pitch and 25-micron wide lines on 40-micron pitch. We have also fabricated embedded inductors, in-plane and in 3-dimension, ranging in values from 750 pH to 42 nH, embedded TaN thin-film resistors with DC values ranging from 10 Ohms to 10 KOhms and embedded capacitors ranging in values from 48 pF to 110 nF measured at 1 MHz and 100 MHz. We have designed, fabricated, characterized and simulated micro-strip lines in a RF module. The transmission losses range from 0.021 to 0.114 dB/mm. The return losses are 25.5 dB to 41 dB and VSWR range from 1.018 to 1.111. We are currently developing the next generation of miniaturized circuits called Integrated System-On-A-Chip. In this technology, Integrated Substrate Technology will be used to stack wafers in 3-D and to make electrical connections through the stacked wafers.
引用
收藏
页码:1232 / 1236
页数:5
相关论文
共 8 条
[1]   The bait in the Rubisco mousetrap [J].
Andrews, TJ .
NATURE STRUCTURAL BIOLOGY, 1996, 3 (01) :3-7
[2]  
BEYNE E, 2000, INT C EXH HIGH DENS, P537
[3]  
GARROU P, 1995, P INT S MICR ISHM LO, P402
[4]  
KULKE R, 2002, P IMAPS NORD STOCKH, P97
[5]  
MESSNER G, 1992, THIN FILM MULTICHIP
[6]  
RAMM P, MICROELECTRONIC ENG, V37, P39
[7]  
SCHAPER LW, 1998, INT J MICROCIRCUITS, V21, P306
[8]   IC stacking technology using fine pitch, nanoscale through silicon vias [J].
Spiesshoefer, S ;
Schaper, L .
53RD ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2003 PROCEEDINGS, 2003, :631-633