Steady-state analysis of phase-locked loops using binary phase detector

被引：7

作者：

Cheng, Shanfeng ^{[1
]}

Tong, Haitao ^{[1
]}

Silva-Martinez, Jose ^{[1
]}

Karsilayan, Aydin Ilker ^{[1
]}

机构：

[1] Texas A&M Univ, Dept Elect & Comp Engn, Analog & Mixed Signal Ctr, College Stn, TX 77843 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2007年 / 54卷 / 06期

关键词：

bang-bang phase detector (BPD); binary phase-detector; clock-and-data recovery (CDR); phase-locked loop (PLL);

D O I：

10.1109/TCSII.2007.894429

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Phase-locked loops (PLLs) using binary phase detectors (BPDs) are modeled and analyzed in this paper. Steady-state behavior for PLLs based on BPDs (BPLs) using first- and second-order loop filters is characterized using transient waveform equations. It is shown that BPLL has a range of oscillation modes in steady state when there is no input jitter. The BPLL is most likely to operate at the most stable oscillation mode (MSOM) under the. disturbance of random input jitter. The MSOM is determined by evaluating the relative stability of all the modes. The expected value of the output jitter amplitude is derived and its dependence on the loop parameters is analyzed.

引用

页码：474 / 478

页数：5

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