3-D Stacked Die: Now or Future?

被引：0

作者：

Bansal, Samta ^{[1
]}

Rey, Juan C. ^{[2
]}

Yang, Andrew ^{[3
]}

Jang, Myung-Soo ^{[4
]}

Lu, L. C. ^{[5
]}

Magarshack, Philippe ^{[6
]}

Pol, Marchal ^{[7
]}

Radojcic, Riko ^{[8
]}

机构：

[1] Cadence, San Jose, CA 95134 USA

[2] Mentor Graph Corp, San Jose, CA USA

[3] Apache Design Solut, San Jose, CA USA

[4] Samsung Elect, Yongin, Gyeonggi Do, South Korea

[5] Taiwan Semicond Mfg Co, Hsinchu, Taiwan

[6] ST Microelect, Crolles, France

[7] IMEC, Leuven, Belgium

[8] Qualcomm, San Diego, CA USA

来源：

PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE | 2010年

关键词：

3-D; integrated circuits;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The continuation of Moore's law by conventional CMOS scaling is becoming challenging. 3D Packaging with 3D through silicon vias (TSV) interconnects is showing promise for extending scaling using mature silicon technology, providing another path towards the "More than Moore". Two years ago, the big unceasing question was "Why 3D?" Today, as we move forward with the concrete implementation of the technology, the questions are now "When 3D?" and How 3D?" There are quite a few brave souls who have taken this disruptive interconnect technology and are investing in it today to gain benefit from it. However, for many the lingering questions remain " Are we there yet?" " Is it now or the future?" This panel brings together key thought leaders in the area of 3D Packaging with 3D TSV interconnects to tell us how they see 3D IC shaping up in the coming year(s) and the challenges that lie ahead associated with TSV in practical design.

引用

页码：298 / 299

页数：2