Sub-1.3 nm amorphous tantalum pentoxide gate dielectrics for damascene metal gate transistors

The formation process of amorphous tantalum pentoxide (Ta2O5) gate dielectrics was developed for sub-0.1 mu m damascene metal gate transistors. Ta2O5 film deposition at high temperature (550 degrees C) on ultrathin (1 nm) oxynitride interface layer improves the surface morphology and decreases the carbon contamination in films. Elimination of post-deposition annealing suppresses the increase of interface layer thickness, and hence, ultrathin equivalent oxide thickness is obtained and good interface characteristics are maintained. The relative dielectric constant of this high-temperature as-deposited film is 26.5 and leakage current reduction of more than two orders of magnitude, compared to that in the case of silicon oxide, is obtained in die sub-2 nm region. A high-performance 90 nm transistor was successfully realized, by applying amorphous Ta2O5 gate dielectrics to damascene metal gate transistor processes. This was due to absence of gate depletion, ultrathin gate dielectrics and excellent interface properties.