Generalized multiplying D/A converter stages for low-power pipelined A/D converters

We present the generalized form of multiplying D/A converter (MDAC) stages in pipelined A/D converters allowing to realize non-integer and integer-valued MDAC gains that are not necessarily in the form of 2(R). This allows better distribution of overall gain among MDAC stages compared to the conventional implementations leading to lower power dissipation. A comprehensive model for estimating the implications on offset voltages of comparators is derived and the impact on error due to capacitive mismatch is analyzed. The general form of digital error correction logic is illustrated. A case study for 65nm technology is elaborated for a 12-bit pipelined converter. The optimization results show that power consumption can be reduced more than 22% by employing non-integer and non-conventional integer gain MDACs for a particular setting.