Design and Characteristics of Digital Locked Loops

Locked loop plays an important role in establishing coherent reference (phase of carrier and symbol timing) in coherent receiver or other regulation systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for the universal multi-mode communication receiver. Afterwards it is necessary to realize both lock loops (phase and symbol timing loops) in synchronizer as digital circuits. Well known characteristics of analog form of loops offer an elegant solution of digital loop design based on the analog template. An analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and methods to determine their characteristics based on analog template are performed in this paper. There are derived transfer responses and error function for the 1(st) order and 2(nd) order digital loops with closed-form expressions. Two ways and equations for the loop filter parameters setting for the 2(nd) order DPLL is presented too. There is shown that the spectrum translation due to sampling process takes indispensable effects in the loop frequency response for specific values of loop parameters.