A Low Power Comparator Design for Analog-to-Digital Converter Using MTSCStack and DTTS Techniques

被引：0

作者：

Krishnan, Pragash Mayar ^{[1
]}

Mustaffa, Mohd Tafir ^{[1
]}

机构：

[1] Univ Sains Malaysia, Sch Elect & Elect Engn, Engn Campus, Nibong Tebal 14300, Pulau Pinang, Malaysia

来源：

9TH INTERNATIONAL CONFERENCE ON ROBOTIC, VISION, SIGNAL PROCESSING AND POWER APPLICATIONS: EMPOWERING RESEARCH AND INNOVATION | 2017年 / 398卷

关键词：

MTSCStack; DTTS; Stacking; Dual threshold; Comparator; Low power;

D O I：

10.1007/978-981-10-1721-6_5

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a low power comparator using Multi Threshold Super Cut-off Stack (MTSCStack) and Dual Threshold Transistor Stacking (DTTS) techniques using a 130 nm CMOS process technology. MTSCStack is proposed in order to decrease the leakage power in active mode and retaining the logic state of the comparator during the idle state. On the other hand, DTSS is proposed to decrease the leakage current with less impact on the delay. Based on the results, the total power consumption especially dynamic power has been reduced significantly by decreasing the VDD of the comparator. The static power and dynamic power of the post-layout proposed comparator is 797 pW and 17.55 mu W respectively with delay of 1.08 ns.

引用

页码：37 / 45

页数：9

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