A Low Power Comparator Design for Analog-to-Digital Converter Using MTSCStack and DTTS Techniques

This paper presents a low power comparator using Multi Threshold Super Cut-off Stack (MTSCStack) and Dual Threshold Transistor Stacking (DTTS) techniques using a 130 nm CMOS process technology. MTSCStack is proposed in order to decrease the leakage power in active mode and retaining the logic state of the comparator during the idle state. On the other hand, DTSS is proposed to decrease the leakage current with less impact on the delay. Based on the results, the total power consumption especially dynamic power has been reduced significantly by decreasing the VDD of the comparator. The static power and dynamic power of the post-layout proposed comparator is 797 pW and 17.55 mu W respectively with delay of 1.08 ns.