Scaling guideline of DRAM memory cells for maintaining the retention time

被引：10

作者：

Ueno, S ^{[1
]}

Inoue, Y ^{[1
]}

Inuishi, M ^{[1
]}

机构：

[1] Mitsubishi Elect Corp, Ulsi Dev Ctr, Itami, Hyogo 6648641, Japan

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852779

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose the model of junction leakage current of local cells. Our model can well explain voltage, temperature dependence and distribution of the leakage current. This model indicates that interface state is considered to control the leakage current and retention time. Based on our model, we found that decreasing the trap density and the electric field are effective for decreasing the leakage current. Moreover, a guideline of trap density, storage capacitance and electric field is proposed for designing future DRAMs to maintain the retention time.

引用

页码：84 / 85

页数：2