Implementation of Reconfigurable Adaptive Filtering Algorithms

Filtering data in real-time requires dedicated hardware to meet demanding time requirements. If the statistics of the signal are not known, then adaptive filtering algorithms can be implemented to estimate the signals statistics iteratively. Modern Field programmable gate arrays (FPGAs) include the resources needed to design efficient filtering structures. This paper aims to combine efficient filter structures with optimized code to create a system-on-programmable-chip (SoPC) solution for various adaptive filtering problems. The algorithms in this paper are implemented using the Cyclone II FPGA device chipped on Altera DE2 board. The inbuilt NIOS II soft core processor of the FPGA device acts as the processor for processing applications. In this paper Least Mean Square (LMS) adaptive filtering algorithm and its variations have been implemented in software and as well as hard ware/software co-design for the NIOS H processor. A comparison is then made between the software implementation and hardware/software co-design implementation. Results obtained show an improvement in the number of clock cycles required when implementing on hardware/software co-design over a pure software implementation. However, using a pure hardware implementation results in a much higher performance with somewhat lower flexibility.