Pentacene is the best performing organic for thin-film field-effect transistor (TFT) applications and its performance rivals that of a-Si:H.(1) We show how to fabricate pentacene TFT with source and drain electrodes lithographically patterned, before the deposition of the pentacene layer on them, and concurrently achieve performance equal to that of TFT fabricated with the reverse layering sequence. We also present a novel method for subtractive patterning of the pentacene layer that does not affect its transport properties. Earlier results on high performance organic TFT at low operating voltage are also presented. TFTs comprising an organic semiconductor layer have been the focus of considerable research activity starting about 15 years ago.(2,3) Such devices based on conjugated polymers, oligomers or other molecules have been fabricated and studied in the past. The mobility of the organic semiconductor thin films is low compared to crystalline Si. However, the demonstrated performance of organic TFT rivals that of hydrogenated amorphous silicon (a-Si:H) TFT. Reviews of the progress in mobility of organic TFT have been published recently.(4,5) Two classes of organic semiconductors have exhibited the best TFT performance accompanied by good environmental stability: end-substituted thiophene oligomers and pentacene. alpha,omega-dihexyl hexathiophene (DH6T), first introduced in organic 6 TFT by Gamier et. al.,(6) is a conjugated oligomer that exhibits a pronounced capacity for self-assembly in close-packed configurations. The highest values of field effect mobility (mu) reported for DH6T films range from 0.07(6) to 0.13(4) cm(2) V(-1) s(-1). Pentacene-based thin film transistors have produced the highest field effect mobility values reported for organic TFT, which in some cases approach 1 cm(2) V(-1) s(-1) with an on/off current ratio of 10(8).(7) These values of mobility and on/off ratio are similar to the ones reported for hydrogenated amorphous silicon (a-Si:H) TFT. However, the operating voltage required to achieve such high performance from pentacene devices is too high (a voltage swing from -100 to +100 V is required). This shortcoming can be demonstrated by comparing the subthreshold slopes of a-Si:H devices (about 0.5 V/decade) and those of pentacene-based TFT, which are about 5-12 V/decade or higher. We have studied the gate voltage dependence of mobility in pentacene devices, and used our understanding to demonstrate high performance pentacene TFTs exhibiting high mobility, good current modulation and excellent subthreshold slopes at low operating voltages.(1,8) For this purpose we employed relatively high dielectric constant metal. oxide films as gate insulators. Furthermore, we developed a room temperature fabrication process that enabled, us to grow such devices on transparent plastic substrates.' The typical device configuration used in our previous work is depicted in Figure 1A. Gold source and drain electrodes were vapor-deposited on pentacene through silicon membrane masks. Pentacene films were deposited using vacuum sublimation. Further details on the vacuum chamber configuration and deposition conditions can be found in reference 4. Relatively high dielectric constant gate insulator layers were deposited on substrates with Pt gate lines using rf magnetron sputtering in the case of barium zirconate titanate (BZT),(1) or were spin-coated by means of a Ba, Sr, Ti isopropanol/acetic acid solution in the case of barium strontium titanate (BST).(8) The latter films were additionally annealed at 400 degreesC in O(2). [GRAPHICS] In order to achieve mobilities of about 0.5 cm(2) V(-1) sec(-1) in pentacene TFTs employing a SiO(2) gate insulator with thickness in the range of 0.1 mum, a gate voltage close to 100 V is required. Figures 2a and 2b show the dependence of field effect mobility, mu, on the charge per unit area at the semiconductor side of the insulator, Q(s), and the gate field, E, respectively. The black circles correspond to a pentacene-based device with a 0.12 mum thick SiO(2) gate Figure 7 provides an explanation for the improvement in device performance. The pentacene grain size on the SAM-modified An is similar to the large grains grown on the SiO(2). There.is no transition region at the An edge. The trap concentration must have beeen drastically reduced. [GRAPHICS] Pentacene is intolerant - after deposition - to exposure to the various chemicals used in typical lithographic processes. Therefore it cannot be patterned using such processes. Usually, shadow masks are used during deposition to-pattern the material. Recently,(11) a technique was proposed which uses topographic discontinuities to isolate the devices. This technique requires that the semiconducting material and the photoresist. remain in inactive areas, which can be a severe limitation for many applications. We have developed a subtractive technique in which pentacene is protected from the consequent lithographic steps by means of a chemically resistant layer. An 1 mum thick layer of parylene-N was used to protect the sensitive pentacene layer from solvents, etchants and other materials used in lithography. The two layer structure thus formed is then etched using a typical lithographic process. Photoresist is spun on top of the structure, and cured. The sample is then exposed through a lithographic mask to UV radiation, and developed. The structure is then etched for 30 minutes in an oxygen plasma, resulting in well defined patterns of protected pentacene on a clean substrate. Pentacene TFT made with this method had performance similar to shadow-mask patterned pentacene.
