Suppression of current collapse by Access-region Carrier Enhancement technique in GaN-MOSFETs

被引：2

作者：

Kajiwara, Y. ^{[1
]}

Ono, H. ^{[1
]}

Kato, D. ^{[1
]}

Shindome, A. ^{[1
]}

Huang, P. C. ^{[1
]}

Wu, P. T. ^{[1
]}

Kuraguchi, M. ^{[1
]}

机构：

[1] Toshiba Co Ltd, Corp Res Dev Ctr, Kawasaki, Kanagawa, Japan

来源：

2022 IEEE 34TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD) | 2022年

关键词：

GaN; MOSFET; current collapse; recessed gate; AlN;

D O I：

10.1109/ISPSD49238.2022.9813605

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Current collapse phenomenon, which is increase of on-resistance caused by high drain voltage at off-state, is a problem to be solved in reliabilities of GaN-based devices. In order to reduce the current collapse, it is necessary to identify traps generated when the drain voltage is applied and reduce the traps. In this paper, we investigate the traps which cause the current collapse by measuring device-capacitance characteristics, and demonstrate that the current collapse is suppressed by a proposed device structure using Access-region Carrier Enhancement (ACE) technique in the Normally-off GaN-MOSFETs. These results show that the proposed GaN-MOSFETs with ACE structure are promising for practical power semiconductor devices.

引用

页码：317 / 320

页数：4