Combining atomic layer deposition with a template-assisted approach to fabricate size-reduced nanowire arrays on substrates and their electrochemical characterization

We report a combinational method to fabricate well-aligned size-reduced gold nanowire (Au NW) arrays on a Si substrate over large areas (> 1.5 cm(2)). In this method, we employ a SiO2 atomic layer deposition (ALD) technique to reduce the pores of a porous anodic alumina (PAA) template which serves as a template for the electrodeposition of Au NW arrays and is directly integrated on the Si substrate. Unlike conventional method that simultaneously reduces the pore size and the interpore spacing by decreasing the applied potential during PAA anodization, our method allows for independently tuning these parameters. By using the ALD-reduced PAA template, we can fabricate the size-reduced Au NW arrays directly on the Si substrate with the average diameter reduced from similar to 79 to similar to 33 nm while their nanowire density and interwire spacing remain constant. The ALD technique enables the fine-tuning of the pore size or the nanowire diameter at an angstrom scale. Electrochemical characterization of the size-reduced Au NW arrays as nanoelectrodes is performed. The double-layer charging current (noise of the nanoelectrodes) decreases with the reduction of the nanowire diameter. Our method could be used to fabricate nanowire arrays with large spacing and small diameters via high voltage anodization and subsequent ALD reduction on the PAA template. This type of nanowire arrays might have potential applications in electrochemical and field-emission devices.