High Throughput Low Power CCMP Architecture for Very High Speed Wireless LANs

被引:0
作者
Hoseini, Seyyed Alireza [1 ]
Khodabandeloo, Behnam [1 ]
Mamaghani, Mandi Jelodari [1 ]
Teymoori, Peyman [1 ]
Yazdani, Nasser [1 ]
机构
[1] Univ Tehran, Dept Elect & Comp Engn, Tehran, Iran
来源
15TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS 2010) | 2010年
关键词
Counter Mode with CBC-MAC Protocol (CCMP); High Speed Wireless LANs; Wireless Security Hardware Architecture; IEEE; 802.11; FRAGMENT RETRANSMISSION; AGGREGATION;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Considering the pervasion of wireless portable devices and growing trends in the use of multimedia applications, access to a high speed and, especially, a high throughput wireless channel are of significant importance. In addition to security concerns in wireless devices, deficiency in throughput and also increase in power consumption are introduced to the system by applying security. Therefore, designing a secure, high-speed wireless device with low power consumption would be a suitable response to worldwide demands. In this paper, we propose a solution to reduce encryption overhead and we almost eliminate it. Furthermore, a customized hardware architecture for Counter Mode with Cipher Block Chaining Message Authentication Code Protocol (CCMP) is proposed. This protocol is the fundamental security architecture of IEEE 802.11i standard. To improve throughput and reduce overhead, encryption is accomplished in the spare time intervals, such as DCF Inter-Frame Spaces (DIFS) used in IEEE 802.11i standard. In order to overcome the restrictions in dealing with these time intervals, a multi-core structure is proposed. Moreover, to reduce power consumption, a particular scheduler is implemented for processing cores. In the proposed architecture, we achieve up to 2Gbps throughput in the single core mode for MPDU (MAC Protocol Data Unit) and A-MSDU (Aggregated MAC Service Data Unit) input frames, and 17Gbps throughput in multi core mode for A-MPDU (Aggregated MPDU) input frames.
引用
收藏
页码:59 / 65
页数:7
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