Low power low noise high speed tunable CMOS radiation detection system

This paper presents a design of low power and low noise, high speed readout front-end system for semiconductor detectors. The architecture comprises a folded cascade charge sensitive amplifier with gain enhancement, a pole-zero cancellation circuit and a complex shaper circuit with Gm-C topology. A local feedback amplifier based on a wide swing gain boosting scheme with dc level shifting has been used. The system has been fabricated in a 0.13-mu m CMOS technology with a single 1.2-V supply voltage. Experimental results show the flexibility of the system where the key parameters, such as decay time, charge gain and peaking time can be tuned. For a nominal peaking time of 150 ns the power consumption of the entire channel is less than 5 mW. A power consumption-low noise tradeoff will be considered to match a detector capacitance of 5 pF. The output pulse has a peak amplitude of 200 mV for a charge of 10 fC from the detector and achieves a linearity better than 1% up to an input charge range of 12 fC. (C) 2013 Elsevier Ltd. All rights reserved.