Low-voltage low-power bulk-driven analog median filter

被引：7

作者：

Khateb, Fabian ^{[1
,2
]}

Kumngern, Montree ^{[3
]}

Dabbous, Salma Bay Abo ^{[1
]}

Kulej, Tomasz ^{[4
]}

机构：

[1] Brno Univ Technol, Dept Microelect, Tech 10, CS-61090 Brno, Czech Republic

[2] Czech Tech Univ, Fac Biomed Engn, Nam Sitna 3105, Kladno, Czech Republic

[3] King Mongkuts Inst Technol Ladkrabang, Fac Engn, Bangkok 10520, Thailand

[4] Czestochowa Tech Univ, Dept Elect Engn, PL-42201 Czestochowa, Poland

来源：

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2016年 / 70卷 / 05期

关键词：

Bulk-driven MOS; Loser-take-all; Median filter; Winner-take-all; FLOATING-GATE; CIRCUITS; DESIGN; ORDER;

D O I：

10.1016/j.aeue.2016.02.007

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents low-voltage (LV) low-power (LP) voltage-mode analog median filter based on winner take-all (WTA) and loser-take-all (LTA) circuits. The LTA and WTA CMOS structures are performed utilizing bulk-driven (BD) MOS transistor (MOST) technique, enabling circuits to operate under low supply voltage of only +/- 0.25 V and consume extremely low-power in micro range. In addition to the simple topology of the proposed circuits, they provide high accuracy. Moreover, the common mode voltage range is near rail to-rail. Eventually, to verify the functionality of the proposed circuits, the simulation results are carried out in Cadence environment using triple-well 0.18 mu m CMOS process. (C) 2016 Elsevier GmbH. All rights reserved.

引用

页码：698 / 706

页数：9

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