3D network-on-chip design for embedded ubiquitous computing systems

被引:6
作者
Wang, Zheng [1 ]
Gu, Huaxi [1 ]
Chen, Yawen [2 ]
Yang, Yintang [3 ]
Wang, Kun [4 ]
机构
[1] Xidian Univ, State Key Lab ISN, Xian, Peoples R China
[2] Univ Otago, Otago, New Zealand
[3] Xidian Univ, Inst Microelect, Xian, Peoples R China
[4] Xidian Univ, Sch Comp Sci & Technol, Xian, Peoples R China
基金
美国国家科学基金会;
关键词
Ubiquitous computing; Networks-on-chip; Multi-cores processors; PATHS;
D O I
10.1016/j.sysarc.2016.10.002
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Ubiquitous High-Performance Computing applications, such as cyber-physical systems, sensor networks and virtual reality require the support of terascale embedded systems that can deliver higher performance than current systems. Multi-cores, many-cores and heterogeneous processors are becoming the typical design choices to satisfy these requirements. Inter core communication has been one of the major challenges as it affects the bandwidth and power consumption of the multi-cores processors. Network-on Chips (NoCs) present a fast and scalable interconnection solution to fulfill the requirements of Ubiquitous High-Performance Computing applications. This paper proposes a novel 3D Network-on-Chip called Octagon for Ubiquitous Computing (OUC) that is designed for Embedded Ubiquitous Computing Systems. OUC provides low network diameter and path diversity. Simulation results show that the proposed topology achieves a significant decrease in latency and an average 21.54% and 12.89% improvement in average throughput under hotspot and uniform traffic pattern respectively. (C) 2016 Elsevier B.V. All rights reserved.
引用
收藏
页码:39 / 46
页数:8
相关论文
共 29 条
  • [1] [Anonymous], OPNET MOD
  • [2] [Anonymous], 2013, 512 MIT CSAIL CSG
  • [3] Networks on chips: A new SoC paradigm
    Benini, L
    De Micheli, G
    [J]. COMPUTER, 2002, 35 (01) : 70 - +
  • [4] A survey of research and practices of network-on-chip
    Bjerregaard, Tobias
    Mahadevan, Shankar
    [J]. ACM COMPUTING SURVEYS, 2006, 38 (01) : 1 - 51
  • [5] Dally W. J., 2004, Principles and Practices of Interconnection Networks
  • [6] Dally WJ, 2001, DES AUT CON, P684, DOI 10.1109/DAC.2001.935594
  • [7] Optimal embeddings of paths with various lengths in twisted cubes
    Fan, Jianxi
    Jia, Xiaohua
    Lin, Xiaola
    [J]. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2007, 18 (04) : 511 - 521
  • [8] Optimal fault-tolerant embedding of paths in twisted cubes
    Fan, Jianxi
    Lin, Xiaola
    Pan, Yi
    Jia, Xiaohua
    [J]. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 2007, 67 (02) : 205 - 214
  • [9] Gu S., 2008, 2008 IEEE INT EL DEV, P1
  • [10] A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
    Howard, Jason
    Dighe, Saurabh
    Vangal, Sriram R.
    Ruhl, Gregory
    Borkar, Nitin
    Jain, Shailendra
    Erraguntla, Vasantha
    Konow, Michael
    Riepen, Michael
    Gries, Matthias
    Droege, Guido
    Lund-Larsen, Tor
    Steibl, Sebastian
    Borkar, Shekhar
    De, Vivek K.
    Van Der Wijngaart, Rob
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (01) : 173 - 183