A 12.5Gbps half-rate CMOS CDR circuit for 10Gbps network applications

被引：4

作者：

Takasoh, J ^{[1
]}

Yoshimura, T ^{[1
]}

Kondoh, H ^{[1
]}

Higashisaka, N ^{[1
]}

机构：

[1] Mitsubishi Electr Corp, High Frequency & Opt Devices Works, Itami, Hyogo 6648641, Japan

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

D O I：

10.1109/VLSIC.2004.1346583

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a true half-rate CMOS CDR circuit suitable for 10Gbps network applications. The CDR adopts a phase detector and a current mode EXOR charge pump with alleviated switching speeds to obtain higher speed margins. A 10.3Gbps CDR for 10Gbps Ethernet has been fabricated using 0.10mum SOI-CMOS process technology. The measured bit error rate of the CDR is less than 10(-12) with a random bit sequence of 2(31)-1. With proposed circuit configuration, the CDR can operate over 12Gbps without error. The jitter tolerance at 10.7Gbps is more than 0.39UIpp with 4M-80MHz jitter frequency range. The input sensitivity is 16mVpp differential. The power dissipation of CDR and 1:2 Deserializer block amounts to 351 mW at a supply voltage of 1.2V.

引用

页码：268 / 271

页数：4