Reconfigurable embedded MAC core design for low-power coarse-grain FPGA

被引：3

作者：

Hong, SJ ^{[1
]}

Chin, SS ^{[1
]}

机构：

[1] SUNY Stony Brook, Dept Elect & Comp Engn, Stony Brook, NY 11794 USA

来源：

ELECTRONICS LETTERS | 2003年 / 39卷 / 07期

关键词：

D O I：

10.1049/el:20030364

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A reconfigurable multiplier design for low-power field programmable gate arrays (FPGAs) is presented. Power consumption reduction is achieved through varying the depth of pipeline of the multiplier. The multiplier incorporates a capability of configuring itself dynamically, thus, is suitable for FPGA type of design.

引用

页码：606 / 608

页数：3

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