共 17 条
[1]
Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI
[J].
MICROELECTRONICS TECHNOLOGY AND DEVICES - SBMICRO 2012,
2012, 49 (01)
:111-118
[2]
Andrade MGC, 2012, ELECTRON, V71, P63, DOI DOI 10.1016/j.sse.2011.10.022
[6]
A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C
[J].
2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS,
2010,
:161-162
[8]
de Andrade M. G. C., 2012, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS), P69, DOI 10.1109/ULIS.2012.6193359
[9]
IMPACT OF SCALING DOWN ON LOW-FREQUENCY NOISE IN SILICON MOS-TRANSISTORS
[J].
PHYSICA STATUS SOLIDI A-APPLIED RESEARCH,
1992, 132 (02)
:501-507
[10]
Han JW, 2006, IEEE NMDC 2006: IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE 2006, PROCEEDINGS, P208