A wide operating frequency range delay-locked loop using a recursive D/A converter

被引:0
|
作者
Lim, Byong-Chan [1 ]
Jo, In-Joon [1 ]
Park, Dong-Soo [1 ]
Hong, Kuk-Tae [1 ]
机构
[1] LG Elect Inc, SIC Biz Team, Circuit Design Gr, Seoul, South Korea
关键词
D O I
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中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A wide operating frequency range, false-lock free delay-locked loop with mixed-mode calibration is presented. The recursive D/A converter in the auxiliary circuit expands the operating frequency range with minimum hardware by controlling the capacitive loading of a delay cell. Moreover, the sampling phase detector with the D/A converter automatically tracks the false-lock free condition. The proposed DLL with equally spaced 14-phase clock outputs is implemented in 0.18 mu m, 3.3V digital CMOS process, and its operating frequency ranges from 15MHz to 270MHz. The measured peak-to-peak jitter and rms jitter at 270MHz are 33.3psec and 3.93psec, respectively. The DLL occupies 0.22mm(2) and consumes 19mA.
引用
收藏
页码:456 / +
页数:2
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