Study on alignment capability and overlay performance in 130nm BEOL lithography process

被引:1
|
作者
Yen, Lau Siau [1 ]
Said, Suhana Mohd [2 ]
Soin, Norhayati [2 ]
Ibrahim, Kader [1 ]
Sang, Ko Bong [1 ]
机构
[1] Silterra Malaysia Sdn Bhd, Kulim 09000, Kedah, Malaysia
[2] Univ Malaya, Dept Elect Engn, Kuala Lumpur 50603, Malaysia
关键词
D O I
10.1109/SMELEC.2006.380703
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
As the device becomes smaller, overlay accuracy requirement is more critical. The wafer alignment is one of the important elements that impact overlay accuracy. In this paper, an evaluation of alignment performance was performed using various alignment marks placed in the scribe-line of short-loop wafers used for SilTerra 130nm process. The alignment capability and overlay performance were studied for Trench I aligns to Contact and Vial aligns to Trench 1, which follows layer-to-layer alignment scheme. A Design of Experiment was conducted with splits in interlayer dielectric (ILD) thickness, tungsten and copper CMP polishing time, in order to evaluate the process sensitivity of multiple alignment marks. Two different types of alignment marks were evaluated. There are Scribe-line Primary Marks (SPM) and Versatile Scribe-line Primary Mark (VSPM). To implement this experiment, exposures were performed using a scanner with various marks and recipes. Then, overlay measurement was conducted on an off-line overlay metrology tool to evaluate the effectiveness of the alignment performance. Data taken by scanner and off-line overlay metrology tool were analysed. The comparison was done between different mark types in an attempt to find out the robust alignment strategy (mark type/color/order) covering all process variation. The results show that, all alignment marks demonstrate low sensitivity to process variation where as there are no wafers were rejected due to alignment error. Besides that, the number of gratings in mark's subdivision for SPM and VSPM affect the signal strength.
引用
收藏
页码:603 / +
页数:3
相关论文
共 50 条
  • [1] Study of reticle cleaning process for 130nm lithography and beyond
    Handa, H
    Takahashi, M
    Shirai, H
    PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY VIII, 2001, 4409 : 430 - 437
  • [2] STUDY OF ALIGNMENT & OVERLAY STRATEGY IN 14 NM LITHOGRAPHY PROCESS
    Lai, Lulu
    Qian, Rui
    Liu, Biqiu
    Guo, Xiaobo
    Zhang, Cong
    Huang, Jun
    Zhang, Yu J.
    2020 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2020 (CSTIC 2020), 2020,
  • [3] Integrated yield enhancement strategy for advanced 130nm BEOL copper process
    Goh, IAN
    Guo, HC
    Zhang, J
    2003 IEEE INTERNATIONAL SYMPOSIUM ON SEMICONDUCTOR MANUFACTURING, CONFERENCE PROCEEDINGS, 2003, : 243 - 246
  • [4] Improvement of Photomask Repeater for 130nm lithography
    Kyoh, S
    Inoue, S
    Mori, I
    Irie, N
    Ishii, Y
    Umatate, T
    Kokubo, H
    Hayashi, N
    PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY VIII, 2001, 4409 : 277 - 286
  • [5] Forbidden pitches for 130nm lithography and below
    Socha, R
    Dusa, M
    Capodieci, L
    Finders, J
    Chen, F
    Flagello, D
    Cummings, K
    OPTICAL MICROLITHOGRAPHY XIII, PTS 1 AND 2, 2000, 4000 : 1140 - 1155
  • [6] Optimization for full chip process of 130nm technology with 248nm DUV lithography
    Ham, YM
    Kim, SK
    Kim, SJ
    Hur, C
    Kim, YS
    Baik, KH
    Kim, BH
    Ahn, DJ
    OPTICAL MICROLITHOGRAPHY XIII, PTS 1 AND 2, 2000, 4000 : 1053 - 1061
  • [7] Impact of attenuated PSM repair for 130nm poly gate lithography process
    Shi, XL
    Hsu, S
    Socha, R
    Chen, F
    Cheng, A
    Su, C
    Cheng, J
    Chen, A
    Lin, H
    Wang, D
    Chen, D
    Lin, A
    Conley, W
    Metzger, D
    Desai, S
    Imamura, PH
    Sherrill, M
    METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XV, 2001, 4344 : 707 - 715
  • [8] Status of ArF lithography for the 130nm technology node
    Ronse, K
    Vandenberghe, G
    Jaenen, P
    Delvaux, C
    Vangoidsenhoven, D
    Van Roey, F
    Pollers, I
    Maenhoudt, M
    Goethals, AM
    Pollentier, I
    Vleeming, B
    Schenau, KV
    Heskamp, B
    Davies, G
    Finders, J
    Niroomand, A
    OPTICAL MICROLITHOGRAPHY XIII, PTS 1 AND 2, 2000, 4000 : 410 - 422
  • [9] GALS Test Chip on 130nm Process
    Bormann, David S.
    ELECTRONIC NOTES IN THEORETICAL COMPUTER SCIENCE, 2006, 146 (02) : 29 - 40
  • [10] Lithography process optimization for 130nm poly gate mask and the impact of mask error factor
    Hsu, S
    Shi, XL
    Socha, RJ
    Chen, JF
    Yee, J
    Ananth, M
    Desai, S
    Imamura, PH
    Sherrill, M
    Tseng, YC
    Chang, HA
    Kao, JF
    Tseng, A
    Liu, WJ
    Chen, A
    Li, A
    Kujten, JP
    Jacobs, E
    Verhappen, A
    METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XV, 2001, 4344 : 783 - 796