Optimal crosstalk shielding insertion along on-chip interconnect trees

Scaling of the on-chip feature size down into the deep submicron range has emphasized the importance of interconnect delay variations due to capacitive coupling. A methodology for reducing crosstalk noise on tree-structured interconnects is proposed in this paper. An algorithm is implemented to compute the optimal sequence of shielding insertion along a capacitively coupled interconnect tree. The reduction in crosstalk is verified through simulation and compared to alternative shielding schemes, considering the availability of limited shielding resources. It is demonstrated that the reduction in interconnect delay variations achieved by the proposed methodology is consistently higher. Furthermore, it is shown that delay variations between two critical nodes in a tree can also be reduced by the same shielding insertion approach.