Transaction level modeling of NoC based multi-processor architecture for wireless communication system

NoC based multi-processor architecture is a solution to satisfy the demand for wireless communication system with higher data rate and multiple standards. It requires fast architecture exploration because it has many options on topologies, protocols, processor granularities, and mapping methodologies. In this paper the transaction level modeling of NoC based multi-processor architecture using SystemC is presented. It requires less effort for initial establishment and guarantees fast simulation speed. In experimental result, it requires 114 times less code-lines to describe more complicated NoC switch and shows 30 similar to 70 times faster simulation speed than RTL simulation.