Extremely scaled high-k/In0.53Ga0.47As gate stacks with low leakage and low interface trap densities

Highly scaled gate dielectric stacks with low leakage and low interface trap densities are required for complementary metal-oxide-semiconductor technology with III-V semiconductor channels. Here, we show that a novel pre-deposition technique, consisting of alternating cycles of nitrogen plasma and tetrakis(dimethylamino) titanium, allows for HfO2 and ZrO2 gate stacks with extremely high accumulation capacitance densities of more than 5 mu F/cm(2) at 1MHz, low leakage current, low frequency dispersion, and low midgap interface trap densities (10(12) cm(-2) eV(-1) range). Using x-ray photoelectron spectroscopy, we show that the interface contains TiO2 and small quantities of In2O3, but no detectable Ga-or As-oxides, or As-As bonding. The results allow for insights into the microscopic mechanisms that control leakage and frequency dispersion in high-k/III-V gate stacks. (C) 2014 AIP Publishing LLC.