Caches and hash trees for efficient memory integrity verification

被引：131

作者：

Gassend, B ^{[1
]}

Suh, GE ^{[1
]}

Clarke, D ^{[1
]}

van Dijk, M ^{[1
]}

Devadas, S ^{[1
]}

机构：

[1] MIT, Comp Sci Lab, Cambridge, MA 02139 USA

来源：

NINTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/HPCA.2003.1183547

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor This verification could enable applications such as certified program execution. A number of schemes are presented with different levels of integration between the on-processor L2 cache and the hash-tree machinery. Simulations show that for the best of our methods, the Performance overhead is less than 25%, a significant decrease from the 10 x overhead of a naive implementation.

引用

页码：295 / 306

页数：12

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