Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets

被引：2

作者：

Chen, Kun ^{[1
,2
,3
]}

Yang, Jingwen ^{[1
]}

Liu, Tao ^{[1
]}

Wang, Dawei ^{[1
]}

Xu, Min ^{[1
,2
,3
]}

Wu, Chunlei ^{[1
,2
,3
]}

Wang, Chen ^{[1
,2
,3
]}

Xu, Saisheng ^{[1
]}

Zhang, David Wei ^{[1
,2
,3
]}

Liu, Wenchao ^{[4
]}

机构：

[1] Fudan Univ, Sch Microelect, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China

[2] Shanghai Integrated Circuit Mfg Innovat Ctr Co Lt, Shanghai 200433, Peoples R China

[3] Zhangjiang Fudan Int Innovat Ctr, Shanghai 200433, Peoples R China

[4] Primarius Technol Co Ltd, Shanghai 201306, Peoples R China

来源：

MICROMACHINES | 2022年 / 13卷 / 07期

关键词：

gate-all-around (GAA); nanosheet (NS); S; D stressor; channel stress enhancement;

D O I：

10.3390/mi13071080

中图分类号：

O65 [分析化学];

学科分类号：

070302 ; 081704 ;

摘要：

A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage ring oscillator (RO) gained up to 27.8% improvement of delay with the same power consumption, for a 3-layer stacked GAA NS-FETs. Furthermore, the proposed S/D trimming technology could enable more than 4-layer vertical stacking of nanosheets for GAA technology extension beyond 3 nm CMOS technology.

引用

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