A Switched-Voltage high-accuracy Sample/Hold circuit

被引：0

作者：

Ohno, K ^{[1
]}

Matsumoto, H ^{[1
]}

Murao, K ^{[1
]}

机构：

[1] Miyazaki Univ, Fac Engn, Circuit Lab, Miyazaki 8892192, Japan

来源：

2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, CONFERENCE PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, three Swicthed-Voltage (SV) Sample/ Hold (S/H) circuits are presented to compensate for clock-feed-through(CFT) and channel-length modulation effect. They consist of a CMOS SV-delay cell. Thus, the configuration is very simple. The proposed circuits can be operated using simple nonoverlapping two phase clocks. The performance is verified by simulations on PSpice.

引用

页码：105 / 108

页数：4