A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS

被引：5

作者：

Chung, Sang-Hye ^{[1
]}

Kim, Young-Ju ^{[2
]}

Kim, Yong-Hun ^{[2
]}

Kim, Lee-Sup ^{[2
]}

机构：

[1] Broadcom Corp, Irvine, CA 92617 USA

[2] Korea Adv Inst Sci & Technol, Dept Elect Engn & Comp Sci, Daejeon 305701, South Korea

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2016年 / 63卷 / 03期

关键词：

Clock deskew; clock recovery; injection-locked oscillator (ILO); jitter filter; jitter mixer; source-synchronous parallel link;

D O I：

10.1109/TCSII.2015.2482400

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents a power-efficient forwarded-clock receiver that is tolerant to high-frequency jitter by mixing filtered clock jitter to data. Due to mixing the filtered clock jitter, the proposed receiver does not include power-hungry delay lines but a phase interpolator, which enables saving significant power consumption. In a prototype receiver implemented in a 1-V 65-nm complementary metal-oxide-semiconductor process, it removes 2-GHz 0.7UI jitter modulated in data by an amount of 22%. It achieves 10 Gb/s with 0.71 pJ/bit in 10-cm FR4 channels and occupies 0.012 mm(2).

引用

页码：264 / 268

页数：5

共 40 条

[1] A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS
Bae, Woorham
Jeong, Gyu-Seob
Jeong, Deog-Kyoon
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63 (12) : 1106 - 1110
[2] A Fully Integrated 1-pJ/bit 10-Gb/s/ch Forwarded-Clock Transmitter with a Resistive Feedback Inverter Based Driver in 65-nm CMOS
Bae, Woorham
Jeong, Gyu-Seob
Jeong, Deog-Kyoon
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 2906 - 2906
[3] A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS
Chung, Sang-Hye
Kim, Lee-Sup
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (10) : 2023 - 2033
[4] A 10 Gb/s Hybrid PLL-based Forwarded Clock Receiver in 65-nm CMOS
Park, Kwanseo
Bae, Woorham
Ju, Haram
Lee, Jinhyung
Jeong, Gyu-Seob
Kim, Yoonsoo
Jeong, Deog-Kyoon
2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2015, : 2389 - 2392
[5] A 2.2-pJ/bit 10-Gb/s Forwarded-Clock Serial-Link Transceiver for IoE Applications
El-Badry, Mohamed
El-Fiky, Mona
Yasser, Aya
Shehata, Ahmed
El-Sayeh, Mostafa
Sallam, Ahmed
Hagras, Mostafa
Abdelati, Ahmed
Ibrahim, Sameh
2017 INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS (ISSCS), 2017,
[6] A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology
Bae, Woorham
Jeong, Gyu-Seob
Park, Kwanseo
Cho, Sung-Yong
Kim, Yoonsoo
Jeong, Deog-Kyoon
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2016, 63 (09) : 1393 - 1403
[7] 10-Gb/s Data Frame Generation Circuit with Frequency Modulation in 65-nm CMOS
Uemura, Hiromu
Furuichi, Kosuke
Koda, Natsuyuki
Inaba, Hiromi
Kishine, Keiji
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2018, 18 (02) : 238 - 245
[8] A 0.36 pJ/bit, 12.5 Gb/s Forwarded-Clock Receiver with a Sample Swapping Scheme and a Half-Bit Delay Line
Bae, Woorham
Jeong, Gyu-Seob
Park, Kwanseo
Cho, Sung-Yong
Kim, Yoonsoo
Jeong, Deog-Kyoon
PROCEEDINGS OF THE 40TH EUROPEAN SOLID-STATE CIRCUIT CONFERENCE (ESSCIRC 2014), 2014, : 447 - +
[9] A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS
Lin, Yu-Chuan
Tsao, Hen-Wai
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2020, 28 (01) : 23 - 34
[10] A 10-Gb/s Power and Area Efficient Clock and Data Recovery Circuit in 65-nm CMOS Technology
Rhim, Jinsoo
Choi, Kwang-Chun
Choi, Woo-Young
2012 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2012, : 104 - 107

← 1 2 3 4 →