+/-1.5V CMOS four-quadrant multiplier

被引：0
|
作者：
Li, SC
机构：
来源：
PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997 | 1996年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A low-voltage CMOS four-quadrant analogue multiplier using two NMOS operated in the triode region with modified hi-directional regulated cascode (RGC) structure is presented. The circuit can operate from a supply voltage of +/- 1.5 V. For a differential input voltage range up to +/- 0.8 V, this circuit has kept nonlinesrity below 0.9 % and total harmonic distortion less than 1 %. The -3 dB bandwidth of this multiplier is 15MHz. The chip was fabricated in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.8 mu m Single-Poly-Double-Metal(SPDM) N-well process. The chip dissipates 24.4 mW and occupies 251 x 653 mu m(2) active area.
引用
收藏
页码：429 / 432
页数：4
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