+/-1.5V CMOS four-quadrant multiplier

被引：0
|
作者：
Li, SC
机构：
来源：
PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997 | 1996年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A low-voltage CMOS four-quadrant analogue multiplier using two NMOS operated in the triode region with modified hi-directional regulated cascode (RGC) structure is presented. The circuit can operate from a supply voltage of +/- 1.5 V. For a differential input voltage range up to +/- 0.8 V, this circuit has kept nonlinesrity below 0.9 % and total harmonic distortion less than 1 %. The -3 dB bandwidth of this multiplier is 15MHz. The chip was fabricated in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.8 mu m Single-Poly-Double-Metal(SPDM) N-well process. The chip dissipates 24.4 mW and occupies 251 x 653 mu m(2) active area.
引用
收藏
页码：429 / 432
页数：4
相关论文
共 50 条
  • [1] 1.5V four-quadrant CMOS current multiplier/divider
    De La Cruz-Blas, CA
    López-Martín, AJ
    Carlosena, A
    ELECTRONICS LETTERS, 2003, 39 (05) : 434 - 436
  • [2] A ±1.5V CMOS four-quadrant analogue multiplier using 3GHz analogue squaring circuits
    Li, SC
    Lin, KL
    ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, 1998, : A347 - A350
  • [3] A 1.5V, wide-input range, high-bandwidth, CMOS four-quadrant analog multiplier
    Sawigun, Chutham
    Mahattanakul, Jirayuth
    PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 2318 - 2321
  • [4] A 1.2 V CMOS four-quadrant analog multiplier
    Hsiao, SY
    Wu, CY
    ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 241 - 244
  • [5] Four-Quadrant CMOS Analog Current Multiplier Using Frequency Compensation and 1.5 V Supply
    Bansal, Urvashi
    Masiwal, Pankaj
    Yadav, Monika
    Mohlia, Mohit
    Raj, Niranjan
    ARABIAN JOURNAL FOR SCIENCE AND ENGINEERING, 2021, 46 (10) : 9849 - 9865
  • [6] A 1.2-V CMOS four-quadrant analog multiplier
    Blalock, BJ
    Jackson, SA
    1999 SOUTHWEST SYMPOSIUM ON MIXED-SIGNAL DESIGN, SSMSD 99, 1999, : 1 - 4
  • [7] Four-Quadrant CMOS Analog Current Multiplier Using Frequency Compensation and 1.5 V Supply
    Urvashi Bansal
    Pankaj Masiwal
    Monika Yadav
    Mohit Mohlia
    Niranjan Raj
    Arabian Journal for Science and Engineering, 2021, 46 : 9849 - 9865
  • [8] Analog CMOS four-quadrant multiplier and divider
    Vlassis, S
    Siskos, S
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 5: SYSTEMS, POWER ELECTRONICS, AND NEURAL NETWORKS, 1999, : 383 - 386
  • [9] A 1.8V CMOS Chopper Four-Quadrant Analog Multiplier
    Baxevanakis, Dimitrios
    Sotiriadis, Paul P.
    2017 6TH INTERNATIONAL CONFERENCE ON MODERN CIRCUITS AND SYSTEMS TECHNOLOGIES (MOCAST), 2017,
  • [10] ±0.5V∼ ±1.5V VHFCMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme
    Li, SC
    Cha, JC
    ISLPED'02: PROCEEDINGS OF THE 2002 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2002, : 227 - 232
12345