An 8-bit 1Gsps CMOS pipeline ADC

被引：1

作者：

Kim, YJ ^{[1
]}

Koo, JH ^{[1
]}

Yun, WJ ^{[1
]}

Lim, SI ^{[1
]}

Kim, S ^{[1
]}

机构：

[1] Korea Univ, Dept Elect, Seoul, South Korea

来源：

PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS | 2004年

关键词：

D O I：

10.1109/APASIC.2004.1349520

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An 8-bit 1Gsamples/s CMOS pipeline ADC(analog to digital converter) is designed with an open loop circuit design technique. To achieve the 1 GHz sampling rate, an interleaving technique is used. To get low power consumption and small die area, common blocks, such as, a reference string, bias blocks, interpolation amplifiers and pre-amplifiers in comparator are shared. At the 1GHz sampling rate, simulation results show that the power consumption is 400mW including digital logic with a power supply of 1.8V and the SNDR of 45dB with an input frequency of 207MHz. The proposed ADC was designed with 0.18um 6-Metal 1-Poly CMOS process and occupies an die area of 800um x 950um. The prototype device is now under fabrication.

引用

页码：424 / 425

页数：2