Improvement of fabrication process for 10-kA/cm2 multi-layer Nb integrated circuits

We have developed an advanced fabrication process for fabricating Nb integrated circuits with up to nine planarized Nb layers, and with critical current density of Josephson junctions of 10 kA/cm(2). We have continued to improve this advanced process. For nine-layer integration, we readjusted film thickness of Nb and SiO2 layers in order to reduce the strain of films and substrate. Total film thickness of the nine-Nb layered structure was about 3 mu m; this was kept nearly as thin as that of the six-Nb-layered structure. The resulting thinner SiO2 layers enabled narrower passive transmission line wiring, which had the advantage of smaller occupation area. The room temperature measurement of process monitoring patterns is useful for screening defective wafers in the middle step of the process. For higher circuit reliability, we modified fabrication processes such as junction planarization. As a result, the reliability of SiO2 insulation between an upper and a lower Nb wire adjacent to a Josephson junction was improved.