A critical path selection method for delay testing

被引：0
|
作者：
Padmanaban, S [1 ]
Tragoudas, S [1 ]
机构：
[1] Intel Corp, Hillsboro, OR 97124 USA
来源：
INTERNATIONAL TEST CONFERENCE 2004, PROCEEDINGS | 2004年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An approach for selecting critical paths along which testable path delay faults can exist is presented. The proposed method is particularly helpful on path intensive circuits. Critical paths are selected implicitly with the aid of a combination of decision diagrams. An implicit method to eliminate untestable faults along the selected paths is also presented. The effectiveness of the approach is demonstrated on path intensive ISCAS'85, ISCAS'89 and ITC'99 benchmarks.
引用
收藏
页码：232 / 241
页数：10
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