A System-in-Package (SiP) With Mounted Input Capacitors for Reduced Parasitic Inductances in a Voltage Regulator

This paper presents a system-in-package (SiP) that mounts an input capacitor for voltage regulators. The SiP has a low power loss of 3.8 W at a switching frequency of 1 MHz, input voltage of 12 V, and output current of 25 A. The parasitic inductance of this SiP is 56% that of the previously reported SiP, which had the input capacitor mounted on the printed circuit board, and this reduction is due to the short current loop from the input capacitor to the MOSFETs. As a result, the power loss can be reduced by 20% for the same spike voltage. The high-side MOSFET die is flipped so that the drain electrode faces up, facilitating the connection of the drain electrode of the high-side MOSFET and the source electrode of the low-side MOSFET to the mounted input capacitor. The authors also propose a way to estimate the parasitic inductance experimentally, not from a current measurement such as with a shunt resistor and a current probe, but from the ringing frequency when the high-side MOSFET is switched and the output capacitance C-OSS of the MOSFET being on the OFF state.